SH7261 Datasheet, PDF (1188/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 User Debugging Interface (H-UDI)
28.3.2 Instruction Register (SDIR)
SDIR is a 16-bit read-only register. It is initialized by UDTRST assertion, in the TAP test-logic-
reset state or in deep standby mode, and can be written to by the H-UDI irrespective of the CPU
mode. Operation is not guaranteed if a reserved command is set in this register. The initial value is
H'EFFD.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TI[7:0]

Initial value: 1* 1* 1* 0* 1* 1* 1* 1* 1
1
1
1
1
1
0
1
R/W: R R R R R R R R R R R R R R R R
Note: * The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to
another value.
Bit
Bit Name Initial Value R/W Description
15 to 8 TI[7:0]
11101111* R
Test Instruction
The H-UDI instruction is transferred to SDIR by a
serial input from UDTDI.
For commands, see table 28.3.
7 to 2 
All 1
R
Reserved
These bits are always read as 1.
1

0
R
Reserved
This bit is always read as 0.
0

1
R
Reserved
This bit is always read as 1.
Note: * The initial value of the TI[7:0] bits is a reserved value. When setting a command, the
TI[7:0] bits must be set to another value.
Table 28.3 H-UDI Commands
Bits 15 to 8
TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description
0
1
1
0
—
—
—
—
H-UDI reset negate
0
1
1
1
—
—
—
—
H-UDI reset assert
1
0
0
1
1
1
0
0
UDTDO change timing switch
1
0
1
1
—
—
—
—
H-UDI interrupt
1
1
1
1
—
—
—
—
BYPASS mode
Other than above
Reserved
Rev. 2.00 Sep. 07, 2007 Page 1156 of 1312
REJ09B0320-0200