SH7261 Datasheet, PDF (28/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

22.4.6 External Trigger Input Timing............................................................................ 1030
22.5 Interrupt Sources and DMAC Transfer Request .............................................................. 1031
22.6 Definitions of A/D Conversion Accuracy........................................................................ 1031
22.7 Usage Notes ..................................................................................................................... 1033
22.7.1 Module Standby Mode Setting ........................................................................... 1033
22.7.2 Setting Analog Input Voltage ............................................................................. 1033
22.7.3 Notes on Board Design ....................................................................................... 1033
22.7.4 Processing of Analog Input Pins......................................................................... 1034
22.7.5 Permissible Signal Source Impedance ................................................................ 1035
22.7.6 Influences on Absolute Precision........................................................................ 1036
22.7.7 Usage Note when Shifting to Single Mode during A/D Conversion .................. 1036
Section 23 D/A Converter (DAC) ................................................................... 1037
23.1 Features............................................................................................................................ 1037
23.2 Input/Output Pins............................................................................................................. 1038
23.3 Register Descriptions....................................................................................................... 1038
23.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)........................................... 1039
23.3.2 D/A Control Register (DACR) ........................................................................... 1039
23.4 Operation ......................................................................................................................... 1041
23.5 Usage Notes ..................................................................................................................... 1042
23.5.1 Module Standby Mode Setting ........................................................................... 1042
23.5.2 D/A Output Hold Function in Software Standby Mode...................................... 1042
23.5.3 D/A Conversion and D/A Output in Deep Standby Mode.................................. 1042
23.5.4 Setting Analog Input Voltage ............................................................................. 1042
Section 24 I/O Ports......................................................................................... 1043
24.1 Port A............................................................................................................................... 1043
24.1.1 Register Configuration........................................................................................ 1044
24.1.2 Port A Data Registers H and L (PADRH and PADRL)...................................... 1044
24.1.3 Port A Port Registers H and L (PAPRH and PAPRL)........................................ 1046
24.2 Port B ............................................................................................................................... 1047
24.2.1 Register Configuration........................................................................................ 1048
24.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ...................................... 1048
24.2.3 Port B Port Registers H and L (PBPRH and PBPRL) ........................................ 1050
24.3 Port C ............................................................................................................................... 1051
24.3.1 Register Configuration........................................................................................ 1051
24.3.2 Port C Data Registers H and L (PCDRH and PCDRL) ...................................... 1052
24.3.3 Port C Port Registers H and L (PCPRH and PCPRL) ........................................ 1053
24.4 Port D............................................................................................................................... 1054
24.4.1 Register Configuration........................................................................................ 1054
Rev. 2.00 Sep. 07, 2007 Page xxviii of xxxii