SH7261 Datasheet, PDF (1007/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.31 Post-ECC Correction Header: Frames (1/75 Seconds) Data Register (HEAD22)
HEAD22 indicates the frames value (1 frame = 1/75 seconds) in the header after ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD22[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
7 to 0 HEAD22[7:0]
Initial
Value R/W Description
All 0 R
Frames value in the header after ECC correction
When MSF_LBA_SEL = 1, this register indicates the
third byte of the total number of sectors calculated
from M, S, and F.
21.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23)
HEAD23 indicates the mode value in the header after ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD23[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
7 to 0 HEAD23[7:0]
Initial
Value R/W Description
All 0 R
Mode value in the header after ECC correction
Rev. 2.00 Sep. 07, 2007 Page 975 of 1312
REJ09B0320-0200