SH7261 Datasheet, PDF (283/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(c) 8-Bit Bus Channel
If an 8-bit bus is selected by the external bus width select bits in the CSn control register, A27 to
A0 are enabled as address signals for byte units. Table 9.9 shows the data alignment
corresponding to byte addresses for different data sizes.
With an 8-bit bus channel only the WR0 pin is enabled, regardless of the strobe mode setting. A
low-level signal is output to WR0 during write access. BC0 constantly outputs low level. Pins
WR3 to WR1 and pins BC3 to BC1 are not used.
Table 9.9 Data Alignment (8-Bit Bus Channel)
Byte Address
DATA
Data Size (Lower 2 Bits) [31:24] [23:16] [15:8] [7:0] [3]
WR/BC
[2] [1] [0]
Byte
0
×
×
×
O
*
*
*
L
1
×
×
×
O
*
*
*
L
2
×
×
×
O
*
*
*
L
3
×
×
×
O
*
*
*
L
Word
0 (1st)
×
×
×
O
*
*
*
L
1 (2nd)
×
×
×
O
*
*
*
L
2 (1st)
×
×
×
O
*
*
*
L
3 (2nd)
×
×
×
O
*
*
*
L
Longword 0 (1st)
×
×
×
O
*
*
*
L
1 (2nd)
×
×
×
O
*
*
*
L
2 (3rd)
×
×
×
O
*
*
*
L
3 (4th)
×
×
×
O
*
*
*
L
Note: The valid bits in the data bus for each data size are indicated by circles (O).
Crosses (×) indicate bus data bits that are undefined.
Asterisks (*) indicate write/byte control bits that are disabled (fixed high level).
Rev. 2.00 Sep. 07, 2007 Page 251 of 1312
REJ09B0320-0200