SH7261 Datasheet, PDF (109/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock
(Pφ), and a bus clock (Bφ). The CPG consists of a crystal oscillator, PLL circuits, and divider
circuits.
4.1 Features
• Three clock operating modes
The mode is selected from among the three clock operating modes by the selection of the
following three conditions: the frequency-divisor in use, whether the PLLs are on or off, and
whether the internal crystal resonator or the input on the external clock-signal line is used.
• Three clocks generated independently
An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip
peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface.
• Frequency change function
Internal and peripheral clock frequencies can be changed independently using the PLL (phase
locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software
using frequency control register (FRQCR) settings.
• Power-down mode control
The clock can be stopped by sleep mode, software standby mode, and deep standby mode.
Specific modules can also be stopped using the module standby function. For details on clock
control in the power-down modes, see section 27, Power-Down Modes.
Rev. 2.00 Sep. 07, 2007 Page 77 of 1312
REJ09B0320-0200