SH7261 Datasheet, PDF(800/1348 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7261 Datasheet, PDF (800/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 17 I2C Bus Interface 3 (IIC3)

(1) Normal case

Synchronous

clock*1

SCL pin

Internally

monitored SCL

VIH

Internal delay*2

Monitored value is high level

Time for

monitoring SCL

(2) When SCL is driven low at first by the slave device

Synchronous

clock*1

SCL pin

Internally

monitored SCL

Slave low

level output

VIH

Internal delay*2

SCL not driven to low level

VIH

Internal delay*2

Monitored value

Monitored value

is high level

Time for is low level

Time for

monitoring SCL

monitoring SCL

Monitored value

is high level

Time for

monitoring SCL

(3) When the rising speed of SCL is slow

Synchronous

clock*1

SCL pin

Internally

monitored SCL

VIH

Internal delay*2

SCL not driven

to low level

Monitored value

Time for

is low level

monitoring SCL

Notes: 1. Clock whose transfer rate is set by bits CKS[3:0] in I2C bus control register 1 (ICCR1).

2. 3 to 4 tpcyc when the NF2CYC bit in NF2CYC is 0 and 4 to 5 tpcyc when the NF2CYC bit is 1.

Figure 17.22 Bit Synchronous Circuit Timing

Rev. 2.00 Sep. 07, 2007 Page 768 of 1312

REJ09B0320-0200

The rate is slower

than the settings.

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