SH7261 Datasheet, PDF (285/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Table 9.10 SDRAMC Commands
Command
SDCS SDRAS SDCAS SDWE
DSL Deselect
H
X
X
X
ACT Initialize row and bank L
L
H
H
RD
Read
L
H
L
H
WR Write
L
H
L
L
PRA Precharge all banks L
L
H
L
RFA Auto-refresh
L
L
L
H
MRS Mode register set
L
L
L
L
EMRS Extended mode
register set
L
L
L
L
RFS Self-refresh entry
L
L
L
H
RFX Self-refresh exit
H
X
X
X
DPD Deep-power-down
L
H
H
L
DPDX Deep-power-down exit X
X
X
X
[Legend]
H: High level, L: Low level, V: Valid, X: Don't care
SDCKE BA1
X
X
H
V
H
V
H
V
H
X
H
X
H
L
H
H
H→L X
L→H X
H→L X
L→H X
BA0
X
V
V
V
X
X
L
L
X
X
X
X
(3) SDRAMC Register Setting Conditions
Rewriting of SDRAMC registers should only be performed when all of the conditions listed in
table 9.11 are satisfied.
Table 9.11 Register Rewrite Conditions
Function/Operation
Self-refresh
Auto-refresh
Initialization sequence
Register
SDRFCNT0
SDRFCNT1
SDIR0
SDIR1
Conditions
• SDRAM access disabled (set in SDRAMCm*¹)
• Auto-refresh enabled (DRFEN = 1)
• Power-down disabled (DPWD/DPWDCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
• Before start of initialization sequence
• After reset or after recovery from deep-power-
down
Rev. 2.00 Sep. 07, 2007 Page 253 of 1312
REJ09B0320-0200