SH7261 Datasheet, PDF (1183/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
27.3.5 Module Standby Function
(1) Transition to Module Standby Function
Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding
on-chip peripheral modules. This function can be used to reduce the power consumption in normal
mode and sleep mode. Disable a module before placing it in the module standby mode. In
addition, do not access the module's registers while it is in the module standby state.
The register states are the same as those in software standby mode.
However, the state of DAC registers are exceptional. In the DAC, all registers retain their previous
values in software standby mode, but are initialized in module standby mode.
(2) Canceling Module Standby Function
The module standby function can be canceled by clearing the MSTP bits to 0, or by a power-on
reset (only possible for RTC, H-UDI, UBC, DMAC, and AUD-II). When taking a module out of
the module standby state by clearing the corresponding MSTP bit to 0, read the MSTP bit to
confirm that it has been cleared to 0.
27.4 Usage Note
27.4.1 Note on Setting Registers
When writing to the registers related to power-down modes, note the following.
When writing to the register related to power-down modes, the CPU, after executing a write
instruction, executes the next instruction without waiting for the write operation to complete.
Therefore, to reflect the change specified by writing to the register while the next instruction is
executed, insert a dummy read of the same register between the register write instruction and the
next instruction.
27.4.2 Note on Canceling Standby Mode when an External Clock is being Input
When release from standby mode is initiated by an interrupt (NMI or IRQ) while an external clock
from the EXTAL pin or CKIO pin is in use, make sure that the external clock is being input before
input of the interrupt. If this is not the case, correct counting of the oscillation settling time will
not be possible.
Rev. 2.00 Sep. 07, 2007 Page 1151 of 1312
REJ09B0320-0200