SH7261 Datasheet, PDF (779/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
17.3.10 NF2CYC Register (NF2CYC)
NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the
SCL and SDA pins. For details of the noise filter, see section 17.4.7, Noise Filter.
NF2CYC is initialized to H'02 by a power-on reset or in deep standby mode.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
NF2
CYC
Initial value: 0
0
0
0
0
0
1
0
R/W: R R R R R R R R/W
Bit
7 to 2
1
0
Bit Name


NF2CYC
Initial
Value
All 0
1
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Reserved
This bit is always read as 0. The write value should
always be 1.
R/W Noise Filtering Range Select
0: The noise less than one cycle of the peripheral clock
can be filtered out
1: The noise less than two cycles of the peripheral clock
can be filtered out
Rev. 2.00 Sep. 07, 2007 Page 747 of 1312
REJ09B0320-0200