SH7261 Datasheet, PDF (725/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.3 SCSMR Settings
n
Clock Source
0
Pφ
1
Pφ/4
2
Pφ/16
3
Pφ/64
CKS1
0
0
1
1
SCSMR Settings
CKS0
0
1
0
1
The bit rate error in asynchronous is given by the following formula:
Error (%) =
Pφ × 10⁶
− 1 × 100
(N + 1) × B × 64 × 2^2n-1
Table 16.4 lists examples of SCBRR settings in asynchronous mode, and table 16.5 lists examples
of SCBRR settings in clocked synchronous mode.
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (1)
Pφ (MHz)
5
6
6.144
Bit Rate
Error
Error
Error
(bit/s)
n N (%) n N (%) n N (%) n
110
2 88 −0.25 2 106 −0.44 2 108 0.08 2
150
2 64 0.16 2 77 0.16 2 79 0.00 2
300
1 129 0.16 1 155 0.16 1 159 0.00 1
600
1 64 0.16 1 77 0.16 1 79 0.00 1
1200
0 129 0.16 0 155 0.16 0 159 0.00 0
2400
0 64 0.16 0 77 0.16 0 79 0.00 0
4800
0 32 −1.36 0 38 0.16 0 39 0.00 0
9600
0 15 1.73 0 19 −2.34 0 19 0.00 0
19200
0 7 1.73 0 9 −2.34 0 9 0.00 0
31250
0 4 0.00 0 5 0.00 0 5 2.40 0
38400
0 3 1.73 0 4 −2.34 0 4 0.00 0
7.3728
Error
N (%)
130 –0.07
95 0.00
191 0.00
95 0.00
191 0.00
95 0.00
47 0.00
23 0.00
11 0.00
6 5.33
5 0.00
Rev. 2.00 Sep. 07, 2007 Page 693 of 1312
REJ09B0320-0200