SH7261 Datasheet, PDF (848/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Table 19.3 Roles of Mailboxes
Tx
Rx
MB15 to MB1 OK
OK
MB0

OK
MB0 (reception MB)
Regiter Name
MB[0].CONTROL0H
MB[0].CONTROL0L
MB[0].LAFMH
MB[0].LAFML
MB[0].MSG_DATA[0][1]
MB[0].MSG_DATA[2][3]
MB[0].MSG_DATA[4][5]
MB[0].MSG_DATA[6][7]
MB[0].CONTROL1H, L
Address
H'100
H'102
H'104
H'106
H'108
H'10A
H'10C
H'10E
H'110
Byte: 8-bit access, Word: 16-bit access, LW (LongWord): 32-bit access
Data Bus
Access Size Field Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDE RTR 0
STDID[10:0]
IDE_
LAFM
0
0
EXTID[15:0]
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
MSG_DATA_0 (first Rx/Tx Byte)
MSG_DATA_2
MSG_DATA_1
MSG_DATA_3
EXTID[17:16]
Word/LW
EXTID_
LAFM[17:16]
Word
Word/LW
Word
Byte/Word/LW
Byte/Word
Control 0
LAFM
Data
MSG_DATA_4
MSG_DATA_5
Byte/Word/LW
MSG_DATA_6
MSG_DATA_7
Byte/Word
0 0 NMC 0 0
MBC[2:0]
000 0
DLC[3:0]
Byte/Word
Control 1
MB1 to 15 (MB for transmission/reception)
Register Name
Address
Data Bus
Access Size
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB[n].CONTROL0H H'100 + n × 32 IDE RTR 0
STDID[10:0]
EXTID[17:16]
Word/LW
MB[n].CONTROL0L
MB[n].LAFMH
MB[n].LAFML
H'102 + n × 32
H'104 + n × 32
IDE_
LAFM
H'106 + n × 32
MB[n].MSG_DATA[0][1] H'108 + n × 32
EXTID[15:0]
00
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
MSG_DATA_0 (first Rx/Tx Byte)
MSG_DATA_1
EXTID_
LAFM[17:16]
Word
Word/LW
Word
Byte/Word/LW
MB[n].MSG_DATA[2][3] H'10A + n × 32
MSG_DATA_2
MSG_DATA_3
Byte/Word
MB[n].MSG_DATA[4][5] H'10C + n × 32
MSG_DATA_4
MSG_DATA_5
Byte/Word/LW
MB[n].MSG_DATA[6][7] H'10E + n × 32
MSG_DATA_6
MSG_DATA_7
Byte/Word
MB[n].CONTROL1H, L H'110 + n × 32 0 0 NMC ATX DART MBC[2:0]
000 0
DLC[3:0]
Byte/Word
Field Name
Control 0
LAFM
Data
Control 1
Notes: 1.
2.
3.
4.
5.
All bits shadowed in grey are reserved and the write value should be 0. The value returned by a read may not always be 0 and should not be relied upon.
MBC1 bit in mailbox is fixed to 1.
ATX and DART are not supported by mailbox-0, and the MBC setting of mailbox-0 is limited.
When the MCR15 bit is 1, the order of STDID, RTR, IDE and EXTID of both message control and LAFM differs from HCAN2.
n = 0 to 15 (mailbox number)
Figure 19.3 Mailbox-n Structure
Rev. 2.00 Sep. 07, 2007 Page 816 of 1312
REJ09B0320-0200