SH7261 Datasheet, PDF (795/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
Master receive mode
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
Dummy-read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Yes
Last receive
- 1?
No
Read ICDRR
Set ACKBT in ICIER to 1
Set RCVD in ICCR1 to 1
Read ICDRR
Read RDRF in ICSR
No
RDRF = 1 ?
Yes
Clear STOP in ICSR
Write 0 to BBSY and SCP
Read STOP in ICSR
No
STOP = 1 ?
Yes
Read ICDRR
Clear RCVD in ICCR1 to 0
Clear MST in ICCR1 to 0
End
[1] Clear TEND, select master receive mode,
and then clear TDRE. *
[1]
[2] Set acknowledge to the transmit device. *
[2]
[3] Dummy-read ICDDR. *
[3] _{[4] Wait for 1 byte to be received}
[5] Check whether it is the (last receive - 1).
[4] [6] Read the receive data.
[7] Set acknowledge of the final byte.
Disable continuous reception (RCVD = 1).
[5]
[8] Read the (final byte - 1) of received data.
[6] _{[9] Wait for the last byte to be receive.}
[10] Clear the STOP flag.
[7] ^{[11] Issue the stop condition.}
[12] Wait for the creation of stop condition.
[8]
[13] Read the last byte of receive data.
[14] Clear RCVD.
[9]
[15] Set slave receive mode.
[10] Notes: * Make sure that no interrupt will be generated during
steps [1] to [3].
[11]
When the size of receive data is only one byte in
reception, steps [2] to [6] are skipped after step [1],
before jumping to step [7].
[12]
The step [8] is dummy-read in ICDRR.
[13]
[14]
[15]
Figure 17.19 Sample Flowchart for Master Receive Mode
Rev. 2.00 Sep. 07, 2007 Page 763 of 1312
REJ09B0320-0200