SH7261 Datasheet, PDF (890/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
(2) Halt mode
When RCAN-ET is in Halt mode, it cannot take part to the CAN bus activity. Consequently the
user can modify all the requested registers without influencing existing traffic on the CAN Bus. It
is important for this that the user waits for the RCAN-ET to be in halt mode before to modify the
requested registers - note that the transition to Halt Mode is not always immediate (transition will
occurs when the CAN Bus is idle or in intermission). After RCAN-ET transit to Halt Mode, GSR4
is set.
Once the configuration is completed the Halt request needs to be released. RCAN-ET will join
CAN Bus activity after the detection of 11 recessive bits on the CAN Bus.
(3) Sleep mode
When RCAN-ET is in sleep mode the clock for the main blocks of the IP is stopped in order to
reduce power consumption. Only the following user registers are clocked and can be accessed:
MCR, GSR, IRR and IMR. Interrupt related to transmission (TXACK and ABACK) and reception
(RXPR and RFPR) cannot be cleared when in sleep mode (as TXACK, ABACK, RXPR and
RFPR are not accessible) and must to be cleared beforehand.
The following diagram shows the flow to follow to move RCAN-ET into sleep mode.
Rev. 2.00 Sep. 07, 2007 Page 858 of 1312
REJ09B0320-0200