SH7261 Datasheet, PDF (563/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 12.76 shows another example of A/D converter start request signal (TRG4AN) operation
when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter start requests
are linked with interrupt skipping.
Note:
This function must be used in combination with interrupt skipping.
When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not
linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR) to 0).
TADCORA_4
TCNT_4
TGIA_3 interrupt
skipping counter
TCIV_4 interrupt
skipping counter
00
00
01
01
02
02
00
00
01
01
TGIA_3 A/D request-enabled
period
TCIV_4 A/D request-enabled
period
A/D converter start request (TRG4AN)
When linked with TGIA_3 and TCIV_4
interrupt skipping
When linked with TGIA_3
interrupt skipping
When linked with TCIV_4
interrupt skipping
(UT4AE/DT4AE = 1)
Note: * When the interrupt skipping count is set to two.
Figure 12.75 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked
with Interrupt Skipping
Rev. 2.00 Sep. 07, 2007 Page 531 of 1312
REJ09B0320-0200