SH7261 Datasheet, PDF (251/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Bit
29, 28
Initial
Bit Name Value
PBCNT[1:0] 00
27, 26 
All 0
25
PWENB 0
24
PRENB
0
23 to 20 
All 0
R/W Description
R/W Page Access Bit Boundary Select
These bits select the bit boundary for page access
operation. When the bit boundary specified by PBCNT
is exceeded during page access, page access
operation is halted temporarily (the CSn signal is
negated), and then page access operation begins
again. The value written to these bits is valid only when
either of the PWENB bit or the PRENB bit is set to 1.
00: 64-bit boundary
01: 128-bit boundary
10: 256-bit boundary
11: Setting prohibited
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Page Write Access Enable
This bit is used to enable page write access.
0: Page write access disabled
1: Page write access enabled
R/W Page Read Access Enable
This bit is used to enable page read access.
0: Page write access disabled
1: Page write access enabled
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 219 of 1312
REJ09B0320-0200