SH7261 Datasheet, PDF (300/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Reset
Specify all SDRAM control pins as port outputs with the PFC
setting of PORTC to output high level
Channel m settings
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Make settings to SDmMOD mode register
(3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR
(4) Set DSZ bits in SDmADR
Perform settings
for all channels
to be used
Enable access
SDRAMCm control register operation enable setting
Dummy-read SDRAM area of all channels to be used
Disable access
SDRAMCm control register operation disable setting
Specify SDRAM control pins (except DQM pin*) as SDRAM
with the PFC setting of PORTC
Initialization sequence
(1) Set DPC, DARFC, and DARFI bits in SDIR0
(2) Set DINIRQ bit in SDIR1 to 1
(3) Wait for DINIST bit in SDIR1 to be cleared to 0
Channel m settings
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Make settings to SDmMOD mode register
(3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR
(4) Set DSZ bits in SDmADR
Perform settings
for all channels
to be used
Start auto-refresh
Set DRFEN bit in SDRFCNT1 to 1
Specify DQM pin as DQM* with the PFC setting of PORTC
Enable access
SDRAMCm control register operation enable setting
SDRAM access enabled
Note : * Driving the DQM pin high before the initialization sequence is recommended
for some SDRAM modules. In this case, the setting may be necessary.
Figure 9.26 SDRAMC Setting Procedure
Rev. 2.00 Sep. 07, 2007 Page 268 of 1312
REJ09B0320-0200