SH7261 Datasheet, PDF (614/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Reset-Synchronized PWM Mode
Figure 12.136 shows an explanatory diagram of the case where an error occurs in PWM mode 1
and operation is restarted in reset-synchronized PWM mode after re-setting.
1
2
3
Power-on TMDR TOER
reset (PWM1) (1)
MTU2
module output
4
5
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
8
9
10
11
12 13
14
15
16
17
18
19
Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
occurs (PORT) (0) (normal) (0 init (disabled) (0)
(RPWM) (1) (MTU2) (1)
0 out)
TIOC3A
TIOC3B
Not initialized (TIOC3B)
TIOC3D
Not initialized (TIOC3D)
Port output
PB16
High-Z
PB17
High-Z
PB19
High-Z
Figure 12.136 Error Occurrence in PWM Mode 1,
Recovery in Reset-Synchronized PWM Mode
1 to 14 are the same as in figure 12.135.
15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with
TOCR.
16. Set reset-synchronized PWM.
17. Enable channel 3 and 4 output with TOER.
18. Set MTU2 output with the PFC.
19. Operation is restarted by TSTR.
Rev. 2.00 Sep. 07, 2007 Page 582 of 1312
REJ09B0320-0200