SH7261 Datasheet, PDF (383/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Table 11.6 Relations between the mode and conditions of DMA transfer.
DMA transfer mode condition
Unit operand
transfer
Sequential operand
transfer
Non-stop transfer
DSEL = "00"
DSEL = "01"
DSEL = "11"
Transfer
mode
Cycle-stealing
transfer
MDSEL = "00"
OK
(between any two
BIUs)
OK
(between any two
BIUs)
OK
(between any two
BIUs)
Pipelined transfer OK
OK
Mainly OK*
MDSEL = "01"
(between any two
BIUs)
(between any two
BIUs)
(between any two
BIUs other than
BIU_E)
Note: * The restriction means that non-stop transfer to the external SDRAM in pipelined
transfer mode cannot be set up.
Rev. 2.00 Sep. 07, 2007 Page 351 of 1312
REJ09B0320-0200