SH7261 Datasheet, PDF (962/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.5 Software Control Flows
20.5.1 Initial Setting
Figure 20.8 shows the flowchart for the initial setting.
Start
[PDCR4 register in PFC setting∗¹]
IERxD, IETxD pins enable
[STBCR2 register setting∗²]
Module stop release
[IECTR register setting]
Pin porarity setting
Receive enable
[IECKSR register setting]
Selection of clock supplied to IEB
[IEAR1, IEAR2 register setting]
Transmission mode
Master address
[IEIET, IEIER register setting]
Interrupt enable
End
Notes: 1. As for setting of PDCR4 register in PFC, see section 25, Pin Function Controller (PFC).
2. As for setting of STBCR2 register, see section 27, Power-Down Modes.
Figure 20.8 Flowchart for Initial Setting
Rev. 2.00 Sep. 07, 2007 Page 930 of 1312
REJ09B0320-0200