SH7261 Datasheet, PDF (51/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Classification Symbol
Direct memory DREQ3 to
access controller DREQ0
(DMAC)
DACK3 to
DACK0
DACT3 to
DACT0
DTEND3 to
DTEND0
Multi-function TCLKA,
timer pulse unit 2 TCLKB,
(MTU2)
TCLKC,
TCLKD
TIOC0A,
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
TIOC1B
TIOC2A,
TIOC2B
TIOC3A,
TIOC3B,
TIOC3C,
TIOC3D
TIOC4A,
TIOC4B,
TIOC4C,
TIOC4D
TIOC5U,
TIOC5V,
TIOC5W
Section 1 Overview
I/O Name
Function
I
DMA-transfer Input pins to receive external
request
requests for DMA transfer
O DMA-transfer
request
acknowledge
Output pins for signals indicating
acknowledge of external requests
from external devices
O DMA-transfer Output pins for signals indicating
request active DMA active in response to external
requests from external devices
O DMA-transfer end Output pins for DMA transfer end
output
I MTU2 timer clock External clock input pins for the timer
input
I/O MTU2 input
capture/output
compare
(channel 0)
I/O MTU2 input
capture/output
compare
(channel 1)
I/O MTU2 input
capture/output
compare
(channel 2)
I/O MTU2 input
capture/output
compare
(channel 3)
I/O MTU2 input
capture/output
compare
(channel 4)
I MTU2 input
capture
(channel 5)
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins.
The TGRA_1 and TGRB_1 input
capture input/output compare
output/PWM output pins.
The TGRA_2 and TGRB_2 input
capture input/output compare
output/PWM output pins.
The TGRA_3 to TGRD_3 input
capture input/output compare
output/PWM output pins.
The TGRA_4 and TGRB_4 input
capture input/output compare
output/PWM output pins.
The TGRU_5, TGRV_5, and
TGRW_5 input capture input/dead
time compensation input pins.
Rev. 2.00 Sep. 07, 2007 Page 19 of 1312
REJ09B0320-0200