SH7261 Datasheet, PDF (651/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
(3) Pin Output
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
16-bit compare match conditions.
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
lower 8-bit compare match conditions.
13.6.2 Compare Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are set to B'100, TCNT_1 counts compare match A for
channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF
flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with
the settings for each channel.
13.7 Interrupt Sources
13.7.1 Interrupt Sources
There are three interrupt sources for the 8-bit timer (TMR_0 or TMR_1): CMIA, CMIB, and OVI.
Their interrupt sources and priorities are shown in table 13.3. Each interrupt source is enabled or
disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt
requests are sent for each to the interrupt controller.
Table 13.3 8-Bit Timer (TMR_0 or TMR_1) Interrupt Sources
Name
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt Source
TCORA_0 compare match
TCORB_0 compare match
TCNT_0 overflow
TCORA_1 compare match
TCORB_1 compare match
TCNT_1 overflow
Interrupt Flag
CMFA
CMFB
OVF
CMFA
CMFB
OVF
Priority
High
Low
High
Low
Rev. 2.00 Sep. 07, 2007 Page 619 of 1312
REJ09B0320-0200