SH7261 Datasheet, PDF (35/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Item
Floating-point Unit
(FPU)
Cache
Features
• Floating-point co-processor included
• Supports single-precision (32-bit) and double-precision (64-bit)
• Supports data type and exceptions that conforms to IEEE754 standard
• Two rounding modes: Round to nearest and round to zero
• Denormalization modes: Flush to zero
• Floating-point registers
Sixteen 32-bit floating-point registers (single-precision × 16 words or
double-precision × 8 words)
Two 32-bit floating-point system registers
• Supports FMAC (multiplication and accumulation) instructions
• Supports FDIV (division) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution time
Latency (FAMC/FADD/FSUB/FMUL): Three cycles (single-precision),
eight cycles (double-precision)
Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six
cycles (double-precision)
Note: FMAC only supports single-precision
• 5-stage pipeline
• Instruction cache: 8 Kbytes
• Operand cache: 8 Kbytes
• 128-entry, 4-way set associative, 16-byte block length configuration
each for the instruction cache and operand cache
• Write-back, write-through and LRU replacement algorithm
• Cache locking function available (only for operand cache); ways 2 and
3 can be locked
Rev. 2.00 Sep. 07, 2007 Page 3 of 1312
REJ09B0320-0200