SH7261 Datasheet, PDF (940/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.3.12 IEBus Receive Message Length Register (IERBFL)
IERBFL indicates the message length field in slave/broadcast reception. This register is enabled
when slave/broadcast receive starts, and the contents are changed at the time of setting the RXS
flag in IERSR.
This register cannot be modified.
IERBFL is initialized by a power-on reset or in deep standby.
Bit: 7
6
5
4
3
2
1
0
RBFL
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit
7 to 0
Initial
Bit Name Value R/W
RBFL
All 0 R
Description
IEBus Receive Message Length
Indicates the contents of the message length field in
slave/broadcast reception.
20.3.13 IEBus Lock Address Register 1 (IELA1)
IELA1 specifies the lower eight bits of a locked address when a unit is locked.
IELA1 is initialized by a power-on reset or in deep standby.
Bit: 7
6
5
4
3
2
1
0
ILAL8
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit
7 to 0
Initial
Bit Name Value R/W
ILAL8
All 0 R
Description
Lower Eight Bits of IEBus Lock Address
Indicates the lower eight bits of the master unit address
when a unit is locked. These bits are valid only when
the LCK bit in IEFLG is set.
Rev. 2.00 Sep. 07, 2007 Page 908 of 1312
REJ09B0320-0200