SH7261 Datasheet, PDF (273/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Bit
7 to 0
Initial
Bit Name Value
DCKSC
[7:0]
H'0F
Section 9 Bus State Controller (BSC)
R/W Description
R/W Clock Stop Control Signal Assert Cycle Count Setting
These bits specify the interval from the point at which
the deep-power-down transition command is issued
until the clock stop signal goes high level to stop the
CKIO (high level), and the interval from the point at
which the clock stop signal goes low level to start the
CKIO operation until the recover command is issued.
00000000: 0 cycle
:
00001111: 15 cycles
:
11111111: 255 cycles
9.4.18 AC Characteristics Switching Register (ACSWR)
When writing to the external address space or making SDRAM settings in power-on reset
exception handling or cancellation of deep standby mode, be sure to set bits ACOSW[3:0] in
ACSWR to B'0011 beforehand.
ACSWR is initialized to H'00000000 by a power-on reset and entry to deep standby mode, but is
not initialized by a manual reset, entry to sleep mode, or entry to software standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————
ACOSW[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 4 
Initial
Value
All 0
R/W Description
R/W Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 241 of 1312
REJ09B0320-0200