SH7261 Datasheet, PDF (808/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
24
DIEN
0
R/W Data Interrupt Enable
0: Data interrupt is disabled.
1: Data interrupt is enabled.
23, 22 CHNL[1:0] 00
R/W Channels
These bits show the number of channels in each
System Word.
00: Having one channel per System Word
01: Having two channels per System Word
10 Having three channels per System Word
11: Having four channels per System Word
21 to 19 DWL[2:0] 000
R/W Data Word Length
Indicates the number of bits in a data word.
000: 8 bits
001: 16 bits
010: 18 bits
011: 20 bits
100: 22 bits
101: 24 bits
110: 32 bits
111: Reserved
18 to 16 SWL[2:0] 000
R/W System Word Length
Indicates the number of bits in a system word.
000: 8 bits
001: 16 bits
010: 24 bits
011: 32 bits
100: 48 bits
101: 64 bits
110: 128 bits
111: 256 bits
Rev. 2.00 Sep. 07, 2007 Page 776 of 1312
REJ09B0320-0200