SH7261 Datasheet, PDF (1334/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions and Additions in this Edition
Item
18.3.2 Status Register (SSISR)
Page Revision (See Manual for Details)
785 Modified
Bit Bit Name Description
0 IDST
:
• SSI = Master transmitter (SWSD = 1
and TRMD = 1)
This bit is set to 1 if the EN bit is
cleared and the data written to
SSITDR is completely output from the
serial data input/output pin (SSIDATA),
that is, the output of the system word
length is completed.
18.4.1 Bus Format
787 Modified
The bus format can be selected from one of the four
major modes shown in table 18.3.
18.4.2 Non-Compressed Modes 793 Modified
(6) Multi-channel Formats
The SSI module supports the transfer of 2, 3 and 4
channels by using the CHNL, SWL and DWL bits only
when the system word length (SWL) is greater than or
equal to the data word length (DWL) multiplied by
channels (CHNL).
18.4.2 Non-Compressed Modes 793 Modified
(6) Multi-channel Formats
Figures 18.7 to 18.9 show how 2, 3 and 4 channels are
transferred to …
Figure 18.7 Multichannel Format 793 Modified
(2 Channels Without Padding)
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 01, SPDP =
don't care, SDTA = don't care
System word length = data word length × 2
Figure 18.8 Multichannel Format 793 Modified
(3 Channels with High Padding)
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 10, SPDP = 1,
SDTA = 0
System word length = data word length × 3
Figure 18.9 Multichannel Format 794 Modified
(4 Channels; Transmitting and
Receiving in
the order of Padding Bits and
Serial Data; with Padding)
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 11, SPDP = 0,
SDTA = 1
System word length = data word length × 4
Rev. 2.00 Sep. 07, 2007 Page 1302 of 1312
REJ09B0320-0200