SH7261 Datasheet, PDF (348/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.5 DMA Reload Destination Address Register (DMRDADR)
DMRDADR is a register used to set an address for reloading to the DMA current destination
address register (DMCDADRn).
To enable reloading, set the DMA destination address reload function enable bit (DRLOD) in
DMA control register A (DMCNTAn) to 1. In this case, set both the DMA current destination
address register (DMCDADRn) and DMA reload destination address register (DMRDADRn).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDA
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RDA
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 0 RDA
Undefined R/W Holds destination address bits A31 to A0 for reloading
Note: Set this register so that DMA transfer is performed within the correctly aligned address
boundaries for the transfer sizes listed below.
• When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
• When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
Rev. 2.00 Sep. 07, 2007 Page 316 of 1312
REJ09B0320-0200