SH7261 Datasheet, PDF (281/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(4) Access Type and Data Alignment
(a) 32-Bit Bus Channel
If a 32-bit bus is selected by the external bus width select bits in the CSn control register, A27 to
A2 are enabled as address signals for longword units and A1 and A0 are disabled (fixed low
level). Table 9.7 shows the data alignment corresponding to byte addresses for different data sizes.
Pins WR3 to WR0 are enabled when byte strobe mode (WRMOD = 0) is selected. Pins BC3 to
BC0 are not used.
Only the WR3 pin is enabled when one-write strobe mode (WRMOD = 1) is selected. A low-level
signal is output from the WR3 pin during write access, regardless of the data size. At this time
pins WR2 to WR0 are disabled (fixed high level). The valid byte positions are indicated by pins
BC3 to BC0.
Table 9.7 Data Alignment (32-Bit Bus Channel)
Byte Address
DATA
Data Size (Lower 2 Bits) [31:24] [23:16] [15:8] [7:0] [3]
WR/BC
[2] [1] [0]
Byte
0
O
×
×
×
L
H
H
H
1
×
O
×
×
H
L
H
H
2
×
×
O
×
H
H
L
H
3
×
×
×
O
H
H
H
L
Word
0
O
O
×
×
L
L
H
H
2
×
×
O
O
H
H
L
L
Longword 0
O
O
O
O
L
L
L
L
Note: The valid bits in the data bus for each data size are indicated by circles (O).
Crosses (×) indicate bus data bits that are undefined.
Rev. 2.00 Sep. 07, 2007 Page 249 of 1312
REJ09B0320-0200