SH7261 Datasheet, PDF (236/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 8 Cache
8.4.4 Notes
1. Programs that access memory-mapped cache should be placed in an address space that is not
cached.
2. Rewriting the address array contents so that two or more ways are hit simultaneously is
prohibited. Operation is not guaranteed if the address array contents are changed so that two or
more ways are hit simultaneously.
3. Memory-mapped cache can be accessed only by the CPU and not by the DMAC. Registers can
be accessed by the CPU and the DMAC.
Rev. 2.00 Sep. 07, 2007 Page 204 of 1312
REJ09B0320-0200