SH7261 Datasheet, PDF (1158/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
Table 27.1 States of Power-Down Modes
State*¹
Power-
Down
Mode
Transition
Conditions
CPU
CPG CPU Register
On-Chip
RAM
On-Chip
Peripheral
Modules
RTC
Power External Canceling
supply Memory Procedure
Sleep
mode
Execute SLEEP
instruction with
STBY bit in STBCR
cleared to 0
Runs Halts Held
Runs
Runs
Runs*² Runs
Auto-
•
refreshing _•
•
•
Interrupt
Manual reset
Power-on reset
Bus error
Software
standby
mode
Execute SLEEP
instruction with
STBY bit in STBCR
set to 1 and DEEP
bit to 0
Halts Halts Held
Halts
(contents
are held)
Halts
Runs*² Runs
Self-
•
refreshing _•
•
•
NMI interrupt
IRQ interrupt
Manual reset
Power-on reset
Deep
standby
mode
Execute SLEEP
Halts Halts Halts
instruction with
STBY and DEEP bits
in STBCR set to 1
Halts
(contents
are
held*³)
Halts
Runs*² Halts
Self-
•
refreshing _•
•
•
NMI interrupt*⁴
IRQ interrupt*⁴ (only
for PE7 to PE4 and
PC25 to PC22)
Manual reset*⁴
Power-on reset*⁴
Module
standby
function
Set the MSTP bits in Runs Runs Held
STBCR2 to STBCR5
to 1
Runs
Specified
module
halts
Halts
Runs
Auto-
•
refreshing _•
Clear MSTP bit to 0
Power-on reset (only
for RTC, H-UDI, UBC,
DMAC, and AUD-II)
Notes: 1. The pin state is retained or set to high impedance. For details, see appendix A, Pin
States.
2. RTC operates when the START bit in the RCR2 register is set to 1. For details, see
section 15, Realtime Clock (RTC).
3. Setting bits RAMKP3 to RAMKP0 in the RAMKP register to 1 enables the retention of
data in the corresponding area in the on-chip RAM during the transition to deep standby
mode. However, when deep standby mode is canceled by a power-on reset, the
contents in the corresponding on-chip RAM area are not retained.
4. Deep standby mode can be canceled by an interrupt (NMI or IRQ) or a reset (manual
reset or power-on reset). However, IRQ is reset only by PE7 to PE0 and PC25 to PC22.
When deep standby mode is canceled by NMI interrupt or IRQ interrupt, reset exception
handling is executed instead of interrupt exception handling. These are power-on reset
exception handlings including a manual reset.
Rev. 2.00 Sep. 07, 2007 Page 1126 of 1312
REJ09B0320-0200