SH7261 Datasheet, PDF (1041/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
• Perform the following processing for seven sectors (indicated by ISEC being generated seven
times) after finding that the LINK_OUT1 bit has been set to 1.
In either of cases 1 and 2 below,
1. LINK_ON = 1 (in the CROMST5 register) is confirmed at each ISEC interrupt, and
LINK_ON = 1 is detected again within the subsequent two-sector period
2. LINK_ON = 1 was not detected at any ISEC interrupt
forcibly stop decoding, set the CROMSY0 register to place the decoder in external sync mode,
and retry decoding by specifying the MSF value stored above + 7 as the MSF value for the
target sector. The start sector address will be the address where RUN_OUT is stored + 7 when
CBUF_LINK = 0, and the address where RUN_OUT is stored when CBUF_LINK = 1.
21.6.4 Reading from the STRMDOUT0 and STRMDOUT1 Registers
When the input stream of data contains an error and ECC correction is executed, the process of
reading from the STRMDOUT0 and STRMDOUT1 registers will be kept waiting by the execution
of ECC correction if the read request is made immediately after an IREADY interrupt or DMA
transfer trigger signal has been generated. This only applies to the first time the registers are read
in the reading of one sector.
In cases where CD-ROM decoding cannot be performed if kept waiting (for example, when the
STRMDOUT0 and STRMDOUT1 registers are read by DMA transfer and input and output for the
SSI are also handled by DMA transfer, so that DMA transfer for the SSI must be carried out with
a fixed period), use the DMAREQDELAY[1:0] bits in the RINGBUFCTL register to delay the
DMA activation signal. This can reduce the length of the wait before reading from the
STRMDOUT0 and STRMDOUT1 registers. Table 21.4 shows the waiting times for the first
reading of STRMDOUT0 and STRMDOUT1 as approximate numbers of cycles. The number of
wait cycles varies according to the positions of any errors for which ECC processing is performed
and so on.
Rev. 2.00 Sep. 07, 2007 Page 1009 of 1312
REJ09B0320-0200