SH7261 Datasheet, PDF (166/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.3.11 DMA Transfer Request Enable Register 1 (DREQER1)
DMA transfer request enable register 1 (DREQER1) is an 8-bit readable/writable register that
enables/disables the SCIF (channels 0 to 3) DMA transfer requests, and enables/disables CPU
interrupt requests.
DMA transfer request enable register 1 is initialized by a power-on reset or in deep standby mode.
Bit: 7
6
5
4
3
2
1
0
SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF
3ch TX 3ch RX 2ch TX 2ch RX 1ch TX 1ch RX 0ch TX 0ch RX
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
7
SCIF 3ch TX 0
R/W DMA Transfer Request Enable Bits
6
SCIF 3ch RX 0
5
SCIF 2ch TX 0
4
SCIF 2ch RX 0
3
SCIF 1ch TX 0
2
SCIF 1ch RX 0
R/W These bits enable/disable DMA transfer requests, and
R/W ^{enable/disable CPU interrupt requests.}
R/W
0: DMA transfer request disabled, CPU interrupt
request enabled
R/W _{1: DMA transfer request enabled, CPU interrupt request}
R/W
disabled
1
SCIF 0ch TX 0
R/W
0
SCIF 0ch RX 0
R/W
Rev. 2.00 Sep. 07, 2007 Page 134 of 1312
REJ09B0320-0200