SH7261 Datasheet, PDF (134/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Exception Handling
Conditions for Transition to Reset State
Internal States
Type
Manual
reset
WDT
RES H-UDI Command MRES Overflow
High Command other Low —
than H-UDI reset
assert is set
High
Command other
than H-UDI reset
assert is set
High
Manual
reset
CPU
Initialized
On-Chip
Peripheral
Modules, I/O Port
Not initialized^*2
WRCSR of
WDT, FRQCR
of CPG
Not initialized
Initialized Not initialized^*2
Not initialized
Notes: 1. Some registers are excluded. For details, see section 30.3, Register States in Each
Operating Mode.
2. The BN bit in IBNR of the INTC is initialized.
5.2.3 Power-On Reset
(1) Power-On Reset by Means of RES Pin
When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this
LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at
power-on or when in software standby mode (when the clock is halted), or at least 20-tcyc when
the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip
peripheral module registers are initialized. See appendix A, Pin States, for the status of individual
pins during the power-on reset state.
In the power-on reset state, power-on reset exception handling starts when the RES pin is first
driven low for a fixed period and then returned to high. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized to 0. The BN bit in IBNR of the INTC is also initialized to 0. FPSCR is initialized to
H'00040001.
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
program begins executing.
Be certain to always perform power-on reset processing when turning the system power on.
Rev. 2.00 Sep. 07, 2007 Page 102 of 1312
REJ09B0320-0200