SH7261 Datasheet, PDF (558/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
data1
TCNT_4
Bit BTE0 in TBTER
Bit BTE1 in TBTER
Buffer register
Data1
(1)
Data2
(3)
Temporary register
Data*
(2)
General register
Data*
Buffer transfer is suppressed
Data2
Data2
[Legend]
(1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period
(bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively).
(2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period.
(3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register.
Note: * When buffer transfer at the crest is selected.
Figure 12.70 Example of Operation when Buffer Transfer is Suppressed
(BTE1 = 0 and BTE0 = 1)
Rev. 2.00 Sep. 07, 2007 Page 526 of 1312
REJ09B0320-0200