SH7261 Datasheet, PDF (926/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.2 Input/Output Pins
Table 20.7 shows the IEB pin configuration.
Table 20.7 Pin Configuration
Name
IEB receive data pin
IEB transmit data pin
Abbreviation I/O
IERxD
I
IETxD
O
Function
Receive data input pin
Transmit data output pin
20.3 Register Descriptions
The IEB has the following registers.
Each register, in principle, has 8-bit width and is accessed in 8 bits.
Table 20.8 Register Configuration
Register Name
Abbrevi-
ation
R/W
IEBus control register
IECTR
R/W
IEBus command register
IECMR
W
IEBus master control register
IEMCR
R/W
IEBus master unit address
register 1
IEAR1
R/W
IEBus master unit address
register 2
IEAR2
R/W
IEBus slave address setting
register 1
IESA1
R/W
IEBus slave address setting
register 2
IESA2
R/W
IEBus transmit message length IETBFL
R/W
register
IEBus reception master address IEMA1
R
register 1
IEBus reception master address IEMA2
R
register 2
Initial
Value
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
Address
H'FFFF1000
H'FFFF1001
H'FFFF1002
H'FFFF1003
Access
Size
8
8
8
8
H'FFFF1004 8
H'FFFF1005 8
H'FFFF1006 8
H'FFFF1007 8
H'FFFF1009 8
H'FFFF100A 8
Rev. 2.00 Sep. 07, 2007 Page 894 of 1312
REJ09B0320-0200