SH7261 Datasheet, PDF (855/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.4 RCAN-ET Control Registers
The following sections describe RCAN-ET control registers. The address is mapped as follow.
Important: These registers can only be accessed in Word size (16-bit).
Table 19.5 RCAN-ET Control Registers Configuration
Description
Master Control Register
General Status Register
Baud Rate Configuration Register 1
Baud Rate Configuration Register 0
Interrupt Request Register
Interrupt Mask Register
Error Counter Register
Address
000
002
004
006
008
00A
00C
Name
MCR
GSR
BCR1
BCR0
IRR
IMR
TEC/REC
Access Size (bits)
Word
Word
Word
Word
Word
Word
Word
19.4.1 Master Control Register (MCR)
The Master Control Register (MCR) is a 16-bit read/write register that controls RCAN-ET.
• MCR (Address = H'000)
Bit: 15 14 13 12
MCR15 MCR14 —
—
Initial value: 1
0
0
0
R/W: R/W R/W R R
11 10 9
8
7
6
5
4
—
TST[2:0]
MCR7 MCR6 MCR5 —
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R
3
2
1
0
— MCR2 MCR1 MCR0
0
0
0
1
R R/W R/W R/W
Bit 15 — ID Reorder (MCR15): This bit changes the order of STDID, RTR, IDE and EXTID of
both message control and LAFM.
Bit15: MCR15
0
1
Description
RCAN-ET is the same as HCAN2
RCAN-ET is not the same as HCAN2 (Initial value)
Rev. 2.00 Sep. 07, 2007 Page 823 of 1312
REJ09B0320-0200