SH7261 Datasheet, PDF (284/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.5.2 SDRAM Interface
A description is provided here of the SDRAM controller (SDRAMC) operation enable and
SDRAM bus width settings as well as operations involving SDRAM (read, write, auto-refresh,
self-refresh, initialization sequence, and mode register settings).
(1) SDRAM Access Enable/Disable and SDRAM Bus Width Settings
Enabling and disabling SDRAM access is performed by making settings in the individual
SDRAMCm control registers to enable or prohibit SDRAMC operation. SDRAM bus width
settings are also performed by means of the SDRAMCm control registers.
Even if the SDRAMC control register is set to disable SDRAMC operation, refresh operation will
still take place if self-refresh or auto-refresh operation is set as enabled.
(2) SDRAM Commands
SDRAMC controls the SDRAM by issuing commands each bus cycle. These commands are
defined by combinations of RAS, CAS, WE, CKE, CS, etc.
Table 9.10 lists the commands issued by SDRAMC.
Rev. 2.00 Sep. 07, 2007 Page 252 of 1312
REJ09B0320-0200