SH7261 Datasheet, PDF (1005/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.27 Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06)
SHEAD06 indicates the sub-mode value in the subheader before ECC correction (byte 22).
Bit: 7
6
5
4
3
2
1
0
SHEAD06[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
Initial
Value R/W Description
7 to 0 SHEAD06[7:0] All 0 R
Sub-mode value in the subheader before ECC
correction (byte 22)
For sectors not in Mode 2, this register contains the
byte of data at the corresponding position.
21.3.28 Pre-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD07)
SHEAD07 indicates the data type value in the subheader before ECC correction (byte 23).
Bit: 7
6
5
4
3
2
1
0
SHEAD07[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
Initial
Value R/W Description
7 to 0 SHEAD07[7:0] All 0 R
Data type value in the subheader before ECC
correction (byte 23)
For sectors not in Mode 2, this register contains the
byte of data at the corresponding position.
Rev. 2.00 Sep. 07, 2007 Page 973 of 1312
REJ09B0320-0200