SH7261 Datasheet, PDF (863/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning.
Bit 1: GSR1
0
1
Description
[Reset condition] When (TEC < 96 and REC < 96) or Bus Off (Initial value)
[Setting condition] When 96 ≤ TEC < 256 or 96 ≤ REC < 256
Note: REC is incremented during Bus Off to count the recurrences of 11 recessive bits as
requested by the Bus Off recovery sequence. However the flag GSR1 is not set in Bus Off.
Bit 0—Bus Off Flag (GSR0): Flag that indicates that RCAN-ET is in the bus off state.
Bit 0: GSR0
0
1
Description
[Reset condition] Recovery from bus off state or after a HW or SW reset
(Initial value)
[Setting condition] When TEC ≥ 256 (bus off state)
Note: Only the lower 8 bits of TEC are accessible from the user interface. The 9^th bit is
equivalent to GSR0.
Rev. 2.00 Sep. 07, 2007 Page 831 of 1312
REJ09B0320-0200