SH7261 Datasheet, PDF (131/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Exception Handling
5.1.3 Exception Handling Vector Table
Before exception handling begins running, the exception handling vector table must be set in
memory. The exception handling vector table stores the start addresses of exception service
routines. (The reset exception handling table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from
which the vector table addresses are calculated. During exception handling, the start addresses of
the exception service routines are fetched from the exception handling vector table, which is
indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3 Exception Handling Vector Table
Exception Sources
Power-on reset
PC
SP
Manual reset
PC
SP
General illegal instruction
(Reserved by system)
Slot illegal instruction
(Reserved by system)
CPU address error
Bus error
Interrupts
NMI
User break
FPU exception
H-UDI
Bank overflow
Bank underflow
Integer division exception (division by zero)
Integer division exception (overflow)
Vector
Numbers
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Vector Table Address Offset
H'00000000 to H'00000003
H'00000004 to H'00000007
H'00000008 to H'0000000B
H'0000000C to H'0000000F
H'00000010 to H'00000013
H'00000014 to H'00000017
H'00000018 to H'0000001B
H'0000001C to H'0000001F
H'00000020 to H'00000023
H'00000024 to H'00000027
H'00000028 to H'0000002B
H'0000002C to H'0000002F
H'00000030 to H'00000033
H'00000034 to H'00000037
H'00000038 to H'0000003B
H'0000003C to H'0000003F
H'00000040 to H'00000043
H'00000044 to H'00000047
H'00000048 to H'0000004B
Rev. 2.00 Sep. 07, 2007 Page 99 of 1312
REJ09B0320-0200