SH7261 Datasheet, PDF (1166/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
27.2.5 Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR5 is initialized to H'FF by a power-on reset or in deep standby mode but
retains its previous value by a manual reset or in software standby mode. Only byte access is valid.
Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP
57 56 55

MSTP MSTP
53 52

CKDV
3
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R R/W R/W R R/W
Initial
Bit
Bit Name Value R/W Description
7
MSTP57 1
R/W Module Stop 57
When the MSTP57 bit is set to 1, the supply of the
clock to the IIC30 is halted.
0: IIC30 runs.
1: Clock supply to IIC30 halted.
6
MSTP56 1
R/W Module Stop 56
When the MSTP56 bit is set to 1, the supply of the
clock to the IIC31 is halted.
0: IIC31 runs.
1: Clock supply to IIC31 halted.
5
MSTP55 1
R/W Module Stop 55
When the MSTP55 bit is set to 1, the supply of the
clock to the IIC32 is halted.
0: IIC32 runs.
1: Clock supply to IIC32 halted.
4

1
R
Reserved
This bit is always read as 1. The write value should
always be 0.
3
MSTP53 1
R/W Module Stop 53
When the MSTP53 bit is set to 1, the supply of the
clock to the SSI0 is halted.
0: SSI0 runs.
1: Clock supply to SSI0 halted.
Rev. 2.00 Sep. 07, 2007 Page 1134 of 1312
REJ09B0320-0200