SH7261 Datasheet, PDF (455/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR_5
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
CMF CMF CMF
U5 V5 W5
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R/(W)*¹R/(W)*¹R/(W)*¹
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
Bit Name
7 to 3 —
2
CMFU5
Initial
Value
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)*¹ Compare Match/Input Capture Flag U5
Status flag that indicates the occurrence of TGRU_5
input capture or compare match.
[Setting conditions]
• When TCNTU_5 = TGRU_5 and TGRU_5 is
functioning as output compare register
• When TCNTU_5 value is transferred to TGRU_5 by
input capture signal while TGRU_5 is functioning as
input capture register
• When TCNTU_5 value is transferred to TGRU_5
while TGRU_5 is functioning as a register for
measuring the pulse width of the external input
signal*².
[Clearing condition]
• When 0 is written to CMFU5 after reading CMFU5 = 1
Rev. 2.00 Sep. 07, 2007 Page 423 of 1312
REJ09B0320-0200