SH7261 Datasheet, PDF (1179/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
Program executing state
Set INTC register as needed
Set RAMKP bit in RAMKP as needed
Execute read and write of an arbitrary
but the same address for each page
in the retaining RAM area.
Set the bits CKS2 to CKS0 in DSCNT
so that the initial value of FRQCR
in the CPG become larger than
the oscillation settling time.
Set the STBY and DEEP bits
in STBCR to 1.
Read STBCR
Clear the flag in DSFR
Interrupt processing routine
Execute SLEEP instruction
Clear the flag in DSFR
Execute RTE instruction
Transition to deep standby mode
Figure 27.2 Flowchart of Transition to Deep Standby Mode
Rev. 2.00 Sep. 07, 2007 Page 1147 of 1312
REJ09B0320-0200