SH7261 Datasheet, PDF (310/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
• Single Write Timing Setting Examples
Figures 9.39 to 9.41 show the correspondence between the timing of single write operations
and the set values of the SDRAMm timing register (SDmTR). Table 9.15 shows the SDRAMm
timing register (SDmTR) set values for each figure.
Table 9.15 SDITR Set Value Correspondence Table (Single Write Timing)
Figure
Figure 9.39
Figure 9.40
Figure 9.41
DRAS
010
000
000
DRCD
00
01
01
DPCG
001
001
001
DWR
0
0
1
Single write
CKIO
SDRAM command
ACT WR DSL PRA DSL
Data bus
d
DRCD
DWR
(ACT-WR) (WR-PRA)
DRAS
(ACT-PRA)
DPCG
(PRA-next)
ACT: Row and bank activation command
WR: Write command
DSL: Deselect command
PRA: Precharge-all command
Note: If the interval set in DRAS is longer than the period from when the WR
command is issued until the DWR interval elapses, the DRAS setting
is used.
Figure 9.39 Single Write Timing Example 1
Rev. 2.00 Sep. 07, 2007 Page 278 of 1312
REJ09B0320-0200