SH7261 Datasheet, PDF (1194/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 Advanced User Debugger II (AUD-II)
(1) Description of Pins
Table 29.2 Description of Pins
Pin
AUDMD
AUDRST
AUDCK
AUDSYNC
AUDATA[3:0]
Function
The mode is selected by changing the input level at this pin.
Low: Setting prohibited
High: RAM monitor mode
The input at this pin should be changed when AUDRST is low.
When this pin is driven low, the AUD enters the reset state and the AUD's
internal buffers and logic are reset. When AUDRST goes high again after the
AUDMD level settles, the AUD starts operating in the selected mode.
This pin is for external clock input. Input the clock to be used for debugging.
Note that the available frequency is up to Bφ/2.
AUD Bus Command Valid Signal
1: Read data is output
0: Inputs write address, data, DIR command
Note: Do not assert this pin until commands are input to AUDATA from
outside and necessary data is prepared. For details, see the protocol
as described later.
The following data is output in time-sharing mode.
• AUD bus command
• Address
• Data
When a command is input from outside, data is output after Ready is
transmitted. The output starts after AUDSYNC is negated. For details, see the
protocol as described later.
Rev. 2.00 Sep. 07, 2007 Page 1162 of 1312
REJ09B0320-0200