SH7261 Datasheet, PDF (1198/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 Advanced User Debugger II (AUD-II)
29.3.3 Usage Notes (RAM Monitor Mode)
(1) Guidelines for initialization of the RAM monitor mode
The buffers in this debugger and the processing status are initialized under the following
conditions.
• Power-on reset
• When the AUDRST pin is driven low
• Module standby
• Deep standby mode
(2) Guidelines for AUDCK
• AUDCK is for inputting the external clock. Input the clock to satisfy Bφ/2 ≥ AUDCK.
(3) Other Limitations
• Do not negate AUDSYNC until the command is input to AUDATA and the Ready is returned.
• The RAM monitor functions in sleep mode but is not available in software standby or deep
standby mode.
Rev. 2.00 Sep. 07, 2007 Page 1166 of 1312
REJ09B0320-0200