SH7261 Datasheet, PDF (1304/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 31 Electrical Characteristics
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
(ACT)
(RD) (RD) (RD) (RD) (PRA)
(ACT)
(RD) (RD) (RD) (RD) (PRA)
CKIO
A16 to A2
A12*
t_AD2 t_AD2
t_AD2 t_AD2 t_AD2 t_AD2 t_AD2
t_AD2
Row
Address
C0 (Column
C1
Address 0)
C2
C3
R1
C4
t_AD2 t_AD2
t_AD2 t_AD2 t_AD2 t_AD2
t_AD2 t_AD2 t_AD2 t_AD2
C5
C6
C7
t_AD2 t_AD2
t_CSD2 t_CSD2 t_CSD2
PRA
command
t_CSD2 t_CSD2 t_CSD2 t_CSD2
PRA
command
t_CSD2
SDCSn
t_RASD t_RASD
t_RASD t_RASD t_RASD t_RASD
t_RASD t_RASD
SDRAS
t_CASD
t_CASD
t_CASD
t_CASD
SDCAS
SDWE
SDCKE
DQMn
t_DQMD
(High)
D31 to D0
t_WED2 t_WED2
t_RDS2 t_RDH2
t_RDS2 t_RDH2
t_WED2 t_WED2
t_RDS2 t_RDH2
t_RDS2 t_RDH2
Note: * Address pin connected to A10 in SDRAM.
Figure 31.19 Multiple Read Row Span Bus Timing for SDRAM Space (Eight Data Access,
DLC = 2 (Two Cycles), DRCD = 1 (Two Cycles), DPCG = 1 (Two Cycles))
Rev. 2.00 Sep. 07, 2007 Page 1272 of 1312
REJ09B0320-0200