SH7261 Datasheet, PDF (1185/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 User Debugging Interface (H-UDI)
Section 28 User Debugging Interface (H-UDI)
This LSI incorporates a user debugging interface (H-UDI) for emulator support.
28.1 Features
The user debugging interface (H-UDI) has reset and interrupt request functions.
The H-UDI in this LSI is used for emulator connection. Refer to the emulator manual for the
method of connecting the emulator.
Figure 28.1 shows a block diagram of the H-UDI.
UDTDI
SDBPR
SDIR
UDTDO
MUX
UDTCK
UDTMS
UDTRST
TAP control circuit
Decoder
Local
bus
[Legend]
SDBPR:
SDIR:
Bypass register
Instruction register
Figure 28.1 Block Diagram of H-UDI
Rev. 2.00 Sep. 07, 2007 Page 1153 of 1312
REJ09B0320-0200