SH7261 Datasheet, PDF (974/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
the wait state. In this case, the IEB waits for data for the maximum number of receive bytes + one
byte. Then, if data for the maximum number of receive bytes + one byte is not received, a receive
timing error is detected and the RXERTME flag is set. In this case, the RXEDLE flag is not set.
The RXEDLE flag is set when data for the maximum number of receive bytes + one byte is
received.
The IEB also waits for data for the maximum number of receive bytes + one byte, when the
maximum number of receive bytes have been received but the parity error is not cleared. If data
for the maximum number of receive bytes + one byte is not received, the RXERTME flag is set. In
this case, the RXEPE flag is not set. The RXEPE flag is set when data for the maximum number
of receive bytes + one byte is received.
Figure 20.19 shows the operation timing when the reception has not been completed within the
maximum number of receive bytes.
IERSR
RXERTME
HD: Header
MA: Master address field
SA: Slave address field
CT: Control field
DL: Message length field
Dn: Data field (n = Max. no. of transfer bytes)
Slave reception
HD MA SA CT DL D1 D2
Dn-1 Dn Dn+1
Dn + 1 is not received
IERSR
RXEDLE
Dn + 1 is received
IERSR
RXEPE
Dn + 1 is received
Figure 20.19 Operation Timing when Reception has not been Completed within Maximum
Number of Receive Bytes
Rev. 2.00 Sep. 07, 2007 Page 942 of 1312
REJ09B0320-0200