SH7261 Datasheet, PDF (255/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.4.6 CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6)
CS2WCNTn specifies the number of wait states and the number of delay cycles.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
CSON[2:0]
—
WDON[2:0]
—
WRON[2:0]
—
RDON[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—————
WDOFF[2:0]
—
CSWOFF[2:0]
—
CSROFF[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
R/W: R R R R R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value
31

0
30 to 28 CSON
000
[2:0]
27

0
26 to 24 WDON 000
[2:0]
23

0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W CS Assert Wait Select
These bits specify the number of wait states inserted
before the external chip select signal (CSn) is asserted.
000: 0 wait state
:
111: 7 wait states
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Write Data Output Wait Select
These bits specify the number of wait states inserted
before data is output to the external data bus.
000: 0 wait state
:
111: 7 wait states
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 223 of 1312
REJ09B0320-0200